Complementary metal oxide semiconductor (CMOS) integrated circuits include both N-type devices (NMOS) and P-type devices (PMOS), the former utilizing electrons as the carriers and the latter utilizing holes as the carriers. CMOS technology is employed in the large majority of integrated circuits manufactured today.
An important factor in the performance of CMOS integrated circuits is the presence of good mobility for both holes and electrons. The mobility of both carriers should be as high as possible to enhance both PMOS and NMOS performance. The overall CMOS circuit performance depends similarly on both NMOS and PMOS performance, and thus in turn, on both electron and hole mobility.
It is known that the application of stress on a semiconductor material, such as silicon, changes the mobility of electrons and holes, which in turn modifies the performance of NMOS and PMOS devices formed thereon. An increase in mobility results in increased performance. However, it has also been found that the electron and hole mobilities do not always react the same way to stress, thereby complicating the process. In addition, the dependence of mobility on stress depends on the surface orientation of the crystalline semiconductor material and the directions of stress and current flow. For example, for current flow along the <110> directions on {100} planes, longitudinal tensile stress tends to increase the mobility of electrons and decrease the mobility of holes. In contrast, for current flow along the <100> directions on {100} planes, longitudinal tensile stress tends to increase the mobility of both electrons and holes.
Currently, semiconductor devices are oriented such that the current flows along the <100> direction on {100} silicon. This can be seen in FIG. 2, which shows a top view of a semiconductor wafer 201. The semiconductor wafer 201 is commonly referred to as “{100} silicon,” which is the predominant type of semiconductor wafer being used today. In the prior art, NMOS and PMOS transistors 203 are oriented in such a manner so that the current flow between source and drain is aligned with the <110> direction, relative to the semiconductor wafer 201. Thus, the transistors 203 are oriented as shown in FIG. 2.
In this orientation, the mobilities of electrons and holes change inversely in reaction to longitudinal stress. In other words, when stress is applied to the underlying silicon along the direction of current flow, either the electron mobility is increased and the hole mobility is decreased or the hole mobility is increased and the electron mobility is decreased. Thus, in such an arrangement, the overall CMOS circuit performance is not enhanced.
For this reason, selective stressing of the silicon material must be employed to increase the carrier mobility of one type of device without degrading the mobility of the other type of device. Thus, stress may be applied to the wafer 201 in the location of transistor 203a, but not transistor 203b, or vice versa. This requires costly processing steps that may include masking, deposition, or etching.